Digital Design and Verification of I3C protocol

Abstract

This thesis presents the design and verification of the MIPI I3C protocol for STMicroelectronics microcontrollers (MCUs), focusing on a complete functional implementation and validation of the protocol. The I3C protocol is a modern serial communication standard that integrates the advantages of I²C and SPI, offering higher speed, improved power efficiency, and dynamic address assignment, making it well-suited for embedded systems and MCU-based applications. The project involves the design, integration, and verification of an I3C Controller that facilitates efficient communication between I3C Targets and Controllers, ensuring data integrity, arbitration handling, and error detection. The design is implemented in Verilog HDL and verified through an extensive testbench environment, incorporating APB-based register access, private messaging, asynchronous FIFOs, and frame management. Functional validation is conducted using simulation and FPGA-based prototyping, ensuring compliance with STMicroelectronics' MCU requirements. Verification is performed using a comprehensive testbench, including APB register read/write operations, private message transactions, and real-time data exchanges. The implementation is evaluated based on protocol compliance, timing performance, and resource utilization, ensuring the design meets the specifications of STMicroelectronics' MCU communication frameworks. The results of this thesis demonstrate a fully functional I3C Controller, successfully Integrated and verified for MCU-based applications, providing a reliable and efficient communication solution. This work contributes to the advancement of I3C Protocol implementations and lays the foundation for future enhancements and optimizations in embedded system designs.